NEW YORK, New York
ASIC DESIGN VERIFICATION ENGINEER Job Opening in NEW YORK, New York - Seeking Design Verification Engineer with 5+ years experience of verification of high-speed ASIC designs. Opportunity is with excellent company providing above market compensation.
Requirement:
- 5+ years Design Verification Experience
- Experience on large, complex high-performance chips (1 GHz or above, many millions of gates, large die sizes) desired
- System Verilog CRV
- Experience one of the following tools: VCS, Questa, or Incisive
- OVM, VMM, or UVM
- Experience with scripting languages: Perl, Python, and/or Tcl.
Relevant methodologies include model checking, equivalence checking, and property checking , and relevant tools include Mentor Questa Formal, Cadence Incisive Formal Verifier (IFV), JasperGold, Synopsys Magellan, and VC Formal.
A Plus to have:
- CDC (Clock domain crossing)
- linting, DRC, Spyglass, DFT (Design for Test), VIP, Verification IP (VIP), low-power emulation
- C++
To apply for this position please submit an MS Word doc of your resume and put in the subject "Job ID # 1809".
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